1. Field of the Invention
The present invention pertains, in general, to package substrates plated without the use of plating lead lines, and manufacturing methods thereof. More specifically, the present invention pertains to a package substrate for electrolytic leadless plating, in which electrolytic Au plating of the package substrate, such as substrate for ball grid array packages (BGA packages) or chip scale packages (CSP), is characterized in that when a semiconductor chip-mounted wire bonding pad and a solder ball pad are formed on the package substrate, the wire bonding pad is subjected to electrolytic leadless Au plating and the solder ball pad is subjected to OSP (Organic Solderability Preservatives) or electroless Au plating without lead lines for use in plating, and a method of manufacturing such a package substrate.
2. Description of the Prior Art
Despite a streamlining trend in the IC (Integrated Circuits) field, for example, high integration, smaller, lighter and higher performance, the number of lead lines used for IC packages is concurrently increasing. With the intention of mounting large numbers of lead lines on a carrier for a small package, the carrier should comprise PGA (Pin Grid Array). Although the PGA carrier has a large number of lead lines mounted on the small carrier, pins or leads are weak and thus are easily broken. Further, limitations are imposed on high-density integration of the circuits.
In order to solve the drawbacks of the PGA substrate, a BGA package substrate has been typically used in recent years, which is advantageous in terms of easy fabrication of a highly dense substrate due to use of solder balls smaller than the pins. Hence, the BGA substrate is used as a package substrate on which a semiconductor chip is mounted.
As shown in FIG. 1, the conventional BGA package substrate comprises solder balls 8, instead of pins. That is, a copper clad laminate (hereinafter, abbreviated to ‘CCL’) 4 is formed with inner layer circuits by a general photo-etching process, and a plurality of CCLs 4 are pressed and laminated. Further, through-holes 2 are formed in the CCL 4, of which the inside of each subjected to Cu plating to form a copper plated layer 3, so that the inner layer circuits are electrically conducted. Then, an outer layer circuit 6 having a bond finger 1 to which a semiconductor chip is joined is externally formed on the CCL 4 by a photo-etching process. As such, together with the outer layer circuit 6, a solder ball pad 7 is formed, to which the solder balls 8 are joined and a solder mask 5 is defined.
When a plating process is performed to increase an electrical connection state of the semiconductor chip-joined bond finger 1 and the solder ball-joined pad 7, the lead lines for use in Au plating are used. Each of the Au plating lead lines is connected to the pad 7 to which a respective solder ball 8 is joined, and at the same time, although not shown in the drawing, the lead lines for use in plating are connected to the pad 7 and further to the bond finger 1 through the through-holes 2. In FIG. 2, there is shown a plan view of a package substrate fabricated in the presence of lead lines for use in plating according to conventional techniques, in which each solder ball 8 is joined to the lead line 9. In FIG. 1, a circled portion ‘A’ denotes a portion formed with the lead lines 9 for use in plating. Substantially, fabrication of high-density circuits is limited attributable to the lead lines.
On the CCL 4 having the outer layer circuit 6 are mounted IC chips, which are connected to the outer layer circuit 6 by means of a conductive wire. A filler is coated on the chips for protection from the external environment. Different from the PGA substrate connected with a main circuit board by means of the pins, the BGA package substrate 10 is electrically conducted with the main circuit board by the solder balls 8 joined to the pad 7 of the CCL 4. Therefore, the BGA is easily miniaturized, compared to the PGA, and thus it is possible to realize high density of the substrate 10.
However, in the conventional package substrate, due to highly dense circuits and miniaturization of a device using such circuits, a pitch (interval between the solder balls) of the solder balls 8 of the BGA package substrate 10 becomes excessively narrow. Simultaneously, circuits around the bond finger 1 onto which the semiconductor chip is mounted become dense. Thus, the lead lines required for Au plating of the bond finger 1 and the pad 7 are difficult to densely form.
Below, a manufacturing process of the package substrate to be Au plated through lead lines for use in plating according to an embodiment of conventional techniques is described, with reference to FIGS. 3a through 3h. 
A plurality of through-holes 13 are formed in a CCL 11+12 as a base substrate (FIG. 3a), and a surface of the base substrate and an inner wall of each through-hole are subjected to Cu plating, to form a Cu plated layer 14 (FIG. 3b).
Then, with the aim of patterning the package substrate, a dry film 15 is coated on the CCL, exposed and then developed (FIG. 3c). The CCL 11+12 comprises an insulation layer 11 and copper foils 12 attached onto a top surface and a bottom surface of the insulation layer 11. Substantially, a plurality of through-holes 13 are formed in the CCL 4 by use of a mechanical drill and are subjected to Cu plating to form the copper plated layer 14, on which a series of processes of coating, exposing and developing the dry film 15 are performed for patterning the substrate.
In FIG. 3d, the copper exposed by use of the dry film 15 as an etching resist is removed with the use of an etching solution. As such, lead lines used for performing later Au plating are also formed. In the drawing, reference numeral 16 denotes an exposed copper-etched portion.
Thereafter, the dry film 15 used as the etching resist is removed using a stripping solution (FIG. 3e).
A solder resist (LPSR) 17 is coated, exposed, developed and then dried on a predetermined portion of the substrate (FIG. 3f).
While an electric current is applied to the lead lines for use in plating, a wire bonding pad and a solder ball pad are subjected to Au plating through the lead lines, to form an Au plated layer 18. As such, a plating process is Ni—Au plating, and the plated Au is 0.5-1.0 μm thick (FIG. 3g).
Specifically, with a view to performing metal finishing of the package substrate, onto which the semiconductor chip is mounted, an electrolytic Au plating process is mainly used because the electrolytic plating process is superior to an electroless Au plating in view of reliability. However, since the lead lines necessary for performing the electrolytic Au plating should be inserted into the substrate, line density is decreased. Thus, it is difficult to fabricate a circuit product having high line density.
The lead lines used for plating are cut either by means of a router or by dicing (FIG. 3h). In the drawing, reference numeral 19 indicates a diced portion. That is, when the lead lines, after the electrolytic Au plating is performed, are cut by the router or by dicing, the lead lines may remain on the package substrate. In such a case, noise is generated upon transmission of electrical signals, thus decreasing electrical performance of the package substrate.
Turning now to FIGS. 4a through 4f, there is sequentially illustrated a manufacturing process of a package substrate to be Au plated in the presence of lead lines for use in plating according to another embodiment of conventional techniques.
In the present embodiment, the step of FIG. 4a is carried out after the steps of FIGS. 3a through 3e mentioned above are performed, and thus a description for the steps of FIGS. 3a through 3e is omitted.
The dry film used as the etching resist is removed as in FIG. 3e, after which a solder resist is coated, exposed, developed and then dried on a predetermined portion of the substrate (FIG. 4a).
In FIG. 4b, a dry film 21 is coated onto the solder ball pad of the substrate, and processes of exposure and development are carried out, so that to only a wire bonding pad is subjected to Au plating.
Then, the wire bonding pad is subjected to Au plating through the lead lines to form a 0.5-1.5 μm thick Au plated layer (FIG. 4c).
The dry film used as a plating resist is removed using a stripping solution (FIG. 4d), and the lead lines used for plating are cut by means of a router or dicing (FIG. 4e). In the drawing, reference numeral 19 indicates a diced portion. That is, after completion of the electrolytic Au plating, the lead lines are cut by the router or by the dicing.
In FIG. 4f, a surface of the solder ball pad is subjected to OSP metal finishing 22.
As such, the lead lines used for plating may remain on the package substrate, and noise is then generated upon transmission of electrical signals, thus lowering electrical performance of the package substrate.
On the other hand, research for electrolytic leadless plating techniques has been carried out by manufacturers of package substrates. In addition, the wire bonding pad or the solder ball pad is subjected to electrolytic Au plating, so that a plated layer having a constant thickness is formed on each pad (plated Au: 0.5-1.5 μm). However, because Au plated on the solder ball pad is thicker than a desired thickness (0.03-0.25 μm), a reliability problem for solder ball bonding is caused.